diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
index e54d564..52c1602 100644
--- a/drivers/block/mvsata_ide.c
+++ b/drivers/block/mvsata_ide.c
@@ -13,6 +13,8 @@
 #include <asm/arch/orion5x.h>
 #elif defined(CONFIG_KIRKWOOD)
 #include <asm/arch/soc.h>
+#elif defined(CONFIG_ARMADA_XP)
+#include <linux/mbus.h>
 #endif
 
 /* SATA port registers */
@@ -90,6 +92,41 @@
 #define MVSATA_STATUS_TIMEOUT	-1
 
 /*
+ * Registers for SATA MBUS memory windows
+ */
+
+#define MVSATA_WIN_CONTROL(w)	(MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4))
+#define MVSATA_WIN_BASE(w)	(MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4))
+
+/*
+ * Initialize SATA memory windows for Armada XP
+ */
+
+#ifdef CONFIG_ARMADA_XP
+static void mvsata_ide_conf_mbus_windows(void)
+{
+	const struct mbus_dram_target_info *dram;
+	int i;
+
+	dram = mvebu_mbus_dram_info();
+
+	/* Disable windows, Set Size/Base to 0  */
+	for (i = 0; i < 4; i++) {
+		writel(0, MVSATA_WIN_CONTROL(i));
+		writel(0, MVSATA_WIN_BASE(i));
+	}
+
+	for (i = 0; i < dram->num_cs; i++) {
+		const struct mbus_dram_window *cs = dram->cs + i;
+		writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
+				(dram->mbus_dram_target_id << 4) | 1,
+				MVSATA_WIN_CONTROL(i));
+		writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
+	}
+}
+#endif
+
+/*
  * Initialize one MVSATAHC port: set SControl's IPM to "always active"
  * and DET to "reset", then wait for SStatus's DET to become "device and
  * comm ok" (or time out after 50 us if no device), then set SControl's
@@ -137,6 +174,10 @@
 	int ret = MVSATA_STATUS_TIMEOUT;
 	int status;
 
+#ifdef CONFIG_ARMADA_XP
+	mvsata_ide_conf_mbus_windows();
+#endif
+
 	/* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
 #if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
 	status = mvsata_ide_initialize_port(